Tathagata Srimani

Assistant Professor, Electrical and Computer Engineering

Bio

Tathagata Srimani is an assistant professor at Carnegie Mellon University, ECE. Previously, he was a postdoctoral scholar in EE at Stanford University. He received the S.M. and the Ph.D. degree in EECS from Massachusetts Institute of Technology in 2018 and 2022 respectively, and the B.Tech degree in E&ECE from IIT Kharagpur in 2016. His research interests include demonstrations of circuits and systems leveraging new nanotechnologies, heterogeneous and monolithic 3D integration, and technology-architecture co-design. His research results include the first silicon fab-compatible process for complementary Carbon Nanotube FETs (CNFETs) (TNANO ’18, ACS Nano ’18) which enabled the first CNFET RISC-V microprocessor (Nature ’19), and the first monolithic 3D system that integrates complementary CNFETs with silicon (Symp. VLSI Tech. ’19, Technology Highlight). His work led to the transition of the first CNFET and CNFET monolithic 3D process to multiple industrial “fabs”: Analog Devices (Nature Electronics ’20) and SkyWater Foundry (Symp. VLSI ’20 – joint technology and circuits focus session; Symp. VLSI’23 – technology focus session + best student paper). He was a recipient of the MIT Presidential Fellowship in 2016 and Morris Joseph Levin Award—best Masterworks (S.M. thesis) presentation at MIT in 2018.

Education

Stanford University, Stanford, CA                                                                            
Postdoctoral Scholar, EE (Jan 2022 – Present)

Massachusetts Institute of Technology, Cambridge, MA                                                                   
PhD, EECS (2022) & SM, EECS (2018)

Indian Institute of Technology, Kharagpur, India                                                                            
Bachelor of Technology (Hons.), Electronics & Electrical Communication (2016)

Research

Low-dimensional nanomaterials, beyond-silicon CMOS technologies, nanofabrication innovation, process-design co-optimization, heterogeneous integration, monolithic 3D (M3D) integration, technology-architecture co-design